SED1374 Datasheet, PDF (64/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 56
Epson Research and Development
Vancouver Design Center
REG[02h] Mode Register 1
Address = FFE2h
Bit-Per-Pixel Bit-Per-Pixel
High
Bit 1
Bit 0
Performance
Input Clock
divide
(CLKI/2)
Display Blank
Frame
Repeat
Read/Write.
Hardware
Video Invert
Enable
Software
Video Invert
bits 7-6
Bit-Per-Pixel Bits [1:0]
These bits select the color or gray-shade depth (Display Mode).
Table 8-2: Gray Shade/Color Mode Selection
Color/Mono
REG[01h] bit 6
0
1
Bit-Per-Pixel Bit 1
REG[02h] bit 7
0
1
0
1
Bit-Per-Pixel Bit 0
REG[02h] bit 6
0
1
0
1
0
1
0
1
Display Mode
2 Gray shade 1 bit-per-pixel
4 Gray shade 2 bit-per-pixel
16 Gray shade 4 bit-per-pixel
reserved
2 Colors
1 bit-per-pixel
4 Colors
2 bit-per-pixel
16 Colors
4 bit-per-pixel
256 Colors 8 bit-per-pixel
bit 5
High Performance (Landscape Modes Only)
When this bit = 0, the internal Memory clock (MCLK) is a divided-down version of the
Pixel clock (PCLK). The denominator is dependent on the bit-per-pixel mode - see the
table below.
Table 8-3: High Performance Selection
High Performance
0
1
BPP Bit 1
0
1
X
BPP Bit 0
0
1
0
1
X
Display Modes
MClk = PClk/8 1 bit-per-pixel
MClk = PClk/4 2 bit-per-pixel
MClk = PClk/2 4 bit-per-pixel
MClk = PClk 8 bit-per-pixel
MClk = PClk
When this bit = 1, MCLK is fixed to the same frequency as PCLK for all bit-per-pixel
modes. This provides a faster screen update performance in 1, 2, 4 bit-per-pixel modes, but
also increases power consumption. This bit can be set to 1 just before a major screen
update, then set back to 0 to save power after the update. This bit has no effect in Swivel-
View mode. Refer to REG[1Bh] SwivelView Mode Register on page 68 for SwivelView
mode clock selection.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29