SED1374 Datasheet, PDF (53/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
7.3.7 Single Color 8-Bit Panel Timing (Format 2)
Page 45
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
VDP
VNDP
LINE1 LINE2 LINE3 LINE4
LINE479 LINE480
LINE1 LINE2
FPLINE
DRDY (MOD)
HDP
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
1-R1 1-B3 1-G6
1-G1 1-R4 1-B6
1-B1 1-G4 1-R7
1-R2 1-B4 1-G7
1-G2 1-R5 1-B7
1-B2 1-G5 1-R8
1-R3 1-B5 1-G8
1-G3 1-R6 1-B8
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
HNDP
1-G638
1-B638
1-R639
1-G639
1-B639
1-R640
1-G640
1-B640
Figure 7-18: Single Color 8-Bit Panel Timing (Format 2)
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02