SED1374 Datasheet, PDF (240/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 8
Epson Research and Development
Vancouver Design Center
2 Installation and Configuration
The SED1374 has five configuration inputs, CNF[4:0], which are read on the rising edge
of RESET# and are fully configurable on this evaluation board. One six-position DIP
switch is provided on the board to configure these five configuration inputs and to
enable/disable hardware power save mode.
The following settings are recommended when using the SDU1374B0C with the ISA bus.
Table 2-1: Configuration DIP Switch Settings
Switch
SW1-1
SW1-2
SW1-3
SW1-4
SW1-5
SW1-6
Signal
CNF0
CNF1
CNF2
CNF3
CNF4
GPIO0
Closed (0 or low)
See “Host Bus Selection” table below
Little Endian
Active low LCDPWR signal
Hardware Suspend Disable
Open (1 or high)
See “Host Bus Selection” table below
Big Endian
Active high LCDPWR signal
Hardware Suspend Enable
= recommended settings (configured for ISA bus support)
S1-3
0
0
0
0
1
1
1
1
1
1
S1-2
0
0
1
1
0
0
1
1
1
1
Table 2-2: Host Bus Selection
S1-1
0
1
0
1
0
1
0
0
1
1
BS#
Host Bus Interface
X
SH-4 bus interface
X
SH-3 bus interface
X
reserved
X
MC68K bus interface #1, 16-bit
X
reserved
X
MC68K bus interface #2, 16-bit
0
reserved
1
reserved
0
Generic #1, 16-bit
1
Generic #2, 16-bit
= recommended settings (configured for ISA bus support)
SED1374
X26A-G-005-01
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26