SED1374 Datasheet, PDF (55/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
7.3.8 Dual Monochrome 8-Bit Panel Timing
Page 47
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
VDP
VNDP
LINE 1/241 LINE 2/242 LINE 3/243 LINE 4/244
LINE 239/479 LINE 240/480
LINE 1/241 LINE 2/242
FPLINE
DRDY (MOD)
HDP
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
1-1
1-5
1 -2
1 -6
1-3
1 -7
1-4
1-8
241-1 241-5
241-2 241-6
241-3 241-7
241-4 241-8
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
HNDP
1 -6 3 7
1 -6 3 8
1 -6 3 9
1 -6 4 0
241-637
241-638
241-639
241-640
Figure 7-20: Dual Monochrome 8-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02