SED1374 Datasheet, PDF (18/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 10
2 Features
Epson Research and Development
Vancouver Design Center
2.1 Integrated Frame Buffer
• Embedded 40K byte SRAM display buffer.
2.2 CPU Interface
• Direct support of the following interfaces:
Hitachi SH-3.
Hitachi SH-4.
Motorola M68K.
MPU bus interface using WAIT# signal.
• Direct memory mapping of internal registers.
• Single level CPU write buffer.
• Registers are mapped into upper 32 bytes of 64K byte address space.
• The complete 40K byte frame buffer is directly and contiguously available through the
16-bit address bus.
2.3 Display Support
• 4/8-bit monochrome LCD interface.
• 4/8-bit color LCD interface.
• Single-panel, single-drive passive displays.
• Dual-panel, dual-drive passive displays.
• Active Matrix TFT / MD-TFD interface
• Register level support for EL panels.
• Example resolutions:
640x480 at a color depth of 1 bpp
640x240 at a color depth of 2 bpp
320x240 at a color depth of 4 bpp
240x160 at a color depth of 8 bpp
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29