SED1374 Datasheet, PDF (387/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

EPSON Research and Development
Vancouver Design Center
Page 13
3.4 SED1374 Configuration
The SED1374 is configured at power up by latching the state of the CNF[4:0] pins. Pin BS# also
plays a role in host bus interface configuration. For details on configuration, refer to the SED1374
Hardware Functional Specification, document number X26A-A-001-xx.
The table below shows those configuration settings relevant to this specific interface.
SED1374
Configuration
Pin
BS#
CNF3
CNF[2:0]
Table 3-3: SED1374 Configuration Using the IT8368E
Value hard wired on this pin is used to configure:
1 (IO V_DD)
Generic #2
Big Endian
111: Generic #1 or #2
0 (V_SS)
Generic #1
Little Endian
= configuration for connection using ITE IT8368E
When the SED1374 is configured for “Generic #1” interface, the host interface pins are mapped as
in the table below.
Table 3-4: SED1374 Generic #1 Interface Pin Mapping
Pin Name Pin Function
WE1#
WE1#
BS#
RD/WR#
connect to V_SS
RD1#
RD#
RD0#
WE0#
WE0#
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09
SED1374
X26A-G-012-01