SED1374 Datasheet, PDF (369/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
4 MCF5307 To SED1374 Interface
Page 13
4.1 Hardware Description
The SED1374 is interfaced to the MCF5307 with a minimal amount of glue logic. One
inverter is required to change the polarity of the WAIT# signal, which is an active low
signal to insert wait states in the bus cycle, while the MCF5307’s Transfer Acknowledge
signal (TA) is an active low signal to end the current bus cycle. The inverter is enabled by
CS# so that TA is not driven by the SED1374 during non-SED1374 bus cycles. A single
resistor is used to speed up the rise time of the WAIT# (TA) signal when terminating the
bus cycle.
The following diagram shows a typical implementation of the MCF5307 to SED1374
interface.
MCF5307
A[16:31]
D[0:15]
CS4
TA
WE3
WE2
OE
BCLK0
RESET
Vcc
470
SED1374
AB[15:0]
DB[15:0]
CS#
WAIT#
WE1#
WE0#
RD/WR#
RD#
BUSCLK
RESET#
Figure 4-1: Typical Implementation of MCF5307 to SED1374 Interface
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-011-02