SED1374 Datasheet, PDF (162/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 66
Epson Research and Development
Vancouver Design Center
/*
** Check the revision code. Exit if we don't find an SED1374.
*/
if (0x18 != *pRegs)
return;
/*
** Initialize the chip.
** Each register is individually programmed to make comments clearer.
*/
/*
** Register 01h: Mode Register 0 - Color, 8-bit format 2
*/
SET_REG(0x01, 0x23);
/*
** Register 02h: Mode Register 1 - 4BPP,
*/
SET_REG(0x02, 0xB0);
High Performance, CLKi/2
/*
** Register 03h: Mode Register 2 - Normal power mode
*/
SET_REG(0x03, 0x03);
/*
** Register 04h: Horizontal Panel Size - 320 pixels - (320/8)-1 = 39 = 27h
*/
SET_REG(0x04, 0x27);
/*
** Register 05h: Vertical Panel Size LSB - 240 pixels
** Register 06h: Vertical Panel Size MSB - (240 - 1) = 239 = EFh
*/
SET_REG(0x05, 0xEF);
SET_REG(0x06, 0x00);
/*
** Register 07h - FPLINE Start Position - not used by STN
*/
SET_REG(0x07, 0x00);
/*
** Register 08h - Horizontal Non-Display Period
**
- HNDP and VNDP are calculated to achieve the
**
desired frame rate according to:
**
**
PCLK
SED1374
X26A-G-002-02
Programming Notes and Examples
Issue Date: 99/04/27