SED1374 Datasheet, PDF (30/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 22
5.3 Summary of Configuration Options
Epson Research and Development
Vancouver Design Center
Configuration
Pin
CNF4
CNF3
CNF[2:0]
Table 5-1: Summary of Power On/Reset Options
Power On/Reset State
1
0
Active high (On) LCDPWR polarity
Active low (On) LCDPWR polarity
Big Endian
Little Endian
Select host bus interface as follows:
CNF2 CNF1 CNF0 BS#
0
0
0
X
0
0
1
X
0
1
0
X
0
1
1
X
1
0
0
X
1
0
1
X
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Host Bus
SH-4 interface
SH-3 interface
reserved
MC68K #1, 16-bit
reserved
MC68K #2, 16-bit
reserved
reserved
Generic #1, 16-bit
Generic #2, 16-bit
5.4 Host Bus Interface Pin Mapping
SED1374
Pin Names
AB[15:1]
AB0
DB[15:0]
WE1#
CS#
BCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
SH-3
A[15:1]
A0
D[15:0]
WE1#
CSn#
CKIO
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#
Table 5-2: Host Bus Interface Pin Mapping
SH-4
MC68K #1
MC68K #2
Generic #1
Generic #2
A[15:1]
A0
D[15:0]
WE1#
CSn#
CKIO
BS#
RD/WR#
RD#
WE0#
RDY#
RESET#
A[15:1]
A[15:1]
A[15:1]
A[15:1]
LDS#
A0
A0
A0
D[15:0]
D[31:16]
D[15:0]
D[15:0]
UDS#
DS#
WE1#
BHE#
External Decode External Decode External Decode External Decode
CLK
CLK
BCLK
BCLK
AS#
R/W#
connect to IO V_DD
connect to IO V_DD
DTACK#
AS#
R/W#
SIZ1
SIZ0
DSACK1#
connect to V_SS
RD1#
RD0#
connect to IO V_DD
connect to IO V_DD
RD#
WE0#
WE#
WAIT#
WAIT#
RESET#
RESET#
RESET#
RESET#
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29