SED1374 Datasheet, PDF (22/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 14
GENERIC #1
BUS
CSn#
A[15:0]
D[15:0]
WE0#
WE1#
RD0#
RD1#
WAIT#
BCLK
RESET#
.
Oscillator
Epson Research and Development
Vancouver Design Center
BS#
CS#
AB[15:0]
DB[15:0]
WE0#
WE1#
RD
RD/WR#
WAIT#
BCLK
RESET#
SED1374
FPDAT[11:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
D[11:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
12-bit
TFT
Display
Figure 3-5: Typical System Diagram (Generic #1 Bus)
.
Oscillator
ISA _REFRESH
BUS SA[19:16]
SA[15:0]
SD[15:0]
SMEMW#
SMEMR#
SBHE#
IOCHRDY
BCLK
RESET
Decoder
BS#
CS#
AB[15:0]
DB[15:0]
WE0#
RD#
WE1#
WAIT#
BCLK
RESET#
SED1374
FPDAT[8:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
LCDPWR
D[8:0]
FPSHIFT
FPFRAME
FPLINE
DRDY
9-bit
TFT
Display
Figure 3-6: Typical System Diagram (Generic #2 Bus - e.g. ISA Bus)
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29