SED1374 Datasheet, PDF (371/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 15
4.3 MCF5307 Chip Select Configuration
Chip Selects 0 and 1 have programmable block sizes from 64K bytes through 2G bytes.
However, these chip selects would normally be needed to control system RAM and ROM.
Therefore, one of the IO chip selects, CS2 through CS7, is required to address the entire
address space of the SED1374. These IO chip selects have a fixed, 2M byte block size. In
the example interface, chip select 4 is used to control the SED1374. The SED1374 only
uses a 64K byte block with its 40K byte display buffer residing at the start of this 64K byte
block and its internal registers occupying the last 32 bytes of this block. This 64K byte
block of memory will be shadowed over the entire 2M byte space. The CSBAR register
should be set to the upper 8 bits of the desired base address.
The following options should be selected in the chip select mask registers (CSMR4/5):
• WP = 0 – disable write protect
• AM = 0 - enable alternate bus master access to the SED1374
• C/I = 1 - disable CPU space access to the SED1374
• SC = 1 - disable Supervisor Code space access to the SED1374
• SD = 0 - enable Supervisor Data space access to the SED1374
• UC = 1 - disable User Code space access to the SED1374
• UD = 0 - enable User Data space access to the SED1374
• V = 1 - global enable (“Valid”) for the chip select
The following options should be selected in the chip select control registers (CSCR4/5):
• WS0-3 = 0 - no internal wait state setting
• AA = 0 - no automatic acknowledgment
• PS (1:0) = 1:0 – memory port size is 16 bits
• BEM = 0 – Byte enable/write enable active on writes only
• BSTR = 0 – disable burst reads
• BSTW = 0 – disable burst writes
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-011-02