SED1374 Datasheet, PDF (350/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 18
Epson Research and Development
Vancouver Design Center
4.3 SED1374 Hardware Configuration
The SED1374 uses CNF4 through CNF0 and BS# to allow selection of the bus mode and
other configuration data on the rising edge of RESET#. Refer to the SED1374 Hardware
Functional Specification, document number X26A-A-001-xx for details.
The tables below show only those configuration settings important to the MPC821
interface. The settings are very similar to the ISA bus with the following exceptions:
• the WAIT# signal is active high rather than active low.
• the Power PC is big endian rather than little endian.
Signal
CNF0
CNF1
CNF2
CNF3
CNF4
Table 4-2: Configuration Settings
Low
High
See “Host Bus Selection” table below See “Host Bus Selection” table below
Little Endian
Active low LCDPWR signal
Big Endian
Active high LCDPWR signal
= configuration for MPC821 host bus interface
CNF2
0
0
0
0
1
1
1
1
1
1
CNF1
0
0
1
1
0
0
1
1
1
1
Table 4-3: Host Bus Selection
CNF0
0
1
0
1
0
1
0
0
1
1
BS#
Host Bus Interface
X
SH-4 interface
X
SH-3 interface
X
reserved
X
MC68K #1, 16-bit
X
reserved
X
MC68K #2, 16-bit
0
reserved
1
reserved
0
Generic #1, 16-bit
1
Generic #2, 16-bit
= configuration for MPC821 host bus interface
SED1374
X26A-G-010-02
Interfacing to the Motorola MPC821 Microprocessor
Issue Date: 99/01/05