SED1374 Datasheet, PDF (414/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 10
Epson Research and Development
Vancouver Design Center
3.2 Generic #2 Interface Mode
Generic #2 Host Bus Interface is a general, non-processor specific interface mode on the
SED1374 that is ideally suited to interface to an 8-bit processor bus.
The interface requires the following signals:
• BUSCLK is a clock input which synchronizes transfers between the host CPU and the
SED1374. It is separate from the input clock (CLKI) and is typically driven by the host
CPU system clock. If the host CPU bus does not provide this clock, an asynchronous
clock can be provided.
• The address inputs AB0 through AB15, and the data bus DB0 through DB15, connect
directly to the CPU address and data bus, respectively. On 32-bit big endian architec-
tures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
Note
In an 8-bit environment D[7:0] must also be connected to D[15:8] respectively
(see Figure 4-1: “Typical Implementation of an 8-bit Processor to the SED1374 Generic
#2 Interface” )
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
memory address space.
• BHE# (WE1#) is the high byte enable for both read and write cycles.
Note
In an 8-bit environment, this signal is driven by inverting address line A0 thus indicating
that odd addresses are to be R/W on the high byte of the data bus.
• WE0# is the enable signal for a write access, to be driven low when the host CPU is
writing the 1374 memory or registers.
• RD# is the read enable for the SED1374, to be driven low when the host CPU is reading
data from the SED1374.
• WAIT# is a signal which is output from the SED1374 to the host CPU that indicates
when data is ready (read cycle) or accepted (write cycle) on the host bus. Since host
CPU accesses to the SED1374 may occur asynchronously to the display update, it is
possible that contention may occur in accessing the 1374 internal registers and/or
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. This signal is active low and may need to be
inverted if the host CPU wait state signal is active high.
• The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus inter-
face for Generic #2 mode. However, BS# is used to configure the SED1374 for
Generic #2 mode and should be tied high (connected to IO V_DD). RD/WR# should also
be tied high.
SED1374
X26A-G-013-01
Interfacing to an 8-bit Processor
Issue Date: 99/05/04