SED1374 Datasheet, PDF (61/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 53
Symbol
Parameter
Min
Typ
Max
t1
Shift Pulse period
1
t2
Shift Pulse pulse width high
0.5
t3
Shift Pulse pulse width low
0.5
t4
Data setup to Shift Pulse falling edge
0.5
t5
Data hold from Shift Pulse falling edge
0.5
t6
Line Pulse cycle time
t7
Line Pulse pulse width low
t8
Frame Pulse cycle time
note 2
9
note 3
t9
Frame Pulse pulse width low
2t6
t10
Horizontal display period
note 4
t11
Line Pulse setup to Shift Pulse falling edge
0.5
t12
Frame Pulse falling edge to Line Pulse falling
edge phase difference
t6 - 18Ts
t13
DRDY to Shift Pulse falling edge setup time
0.5
t14
DRDY pulse width
note 5
t15
DRDY falling edge to Line Pulse falling edge
note 6
t16
DRDY hold from Shift Pulse falling edge
0.5
t17
Line Pulse Falling edge to DRDY active
note 7
250
1. Ts = pixel clock period
2. t6min = [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0)+4) x 8] Ts
3. t8 min = [((REG[06h] bits 1-0, REG[05h] bits 7-0)+1) + (REG[0Ah] bits 6-0)] Lines
4. t10min = [((REG[04h] bits 6-0)+1) x 8] Ts
5. t14min = [((REG[04h] bits 6-0)+1) x 8] Ts
6. t15min = [(REG[07h] bits 4-0) x 8 + 16] Ts
7. t17min = [(REG[08h] bits 4-0) - (REG[07]) x 8 + 16] Ts
Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02