SED1374 Datasheet, PDF (41/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
7.1.6 Generic #2 Interface Timing
T_BCLK
BCLK
A[15:0]
BHE#
VALID
Page 33
CS#
t1
t2
WE#,RD#
D[15:0]
(write)
D[15:0]
(read)
WAIT#
t3
Hi-Z
t5
Hi-Z
t8
Hi-Z
VALID
t6
t9
VALID
t4
t7
Hi-Z
t10
Hi-Z
Figure 7-6: Generic #2 Timing
Symbol
f_BCLK
T_BCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Table 7-6: Generic #2 Timing
Parameter
Bus Clock frequency
Bus Clock period
A[15:0], BHE#, CS# valid to WE#, RD# low
WE#, RD# high to A[15:0], BHE#, CS# invalid
WE# low to D[15:0] valid (write cycle)
WE# high to D[15:0] invalid (write cycle)
RD# low to D[15:0] driven (read cycle)
D[15:0] valid to WAIT# high (read cycle)
RD# high to D[15:0] high impedance (read cycle)
WE#, RD# low to WAIT# driven low
BCLK to WAIT# high
WE#, RD# high to WAIT# high impedance
Min
0
1/f_BCLK
0
0
0
0
Max
50
T_BCLK
16
10
14
16
11
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
BCLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 86
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02