SED1374 Datasheet, PDF (131/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 35
6.3 LCD Enable/Disable
The descriptions below cover manually powering the LCD panel up and down. Use them
only if the power supply connected to the panel requires more than 127 frames to discharge
on power-down or if the panel requires starting the LCD logic well in advance of enabling
LCD power.
Power On/Enable Sequence
The following is the recommended sequence for manually powering-up an LCD panel.
These steps would be used if LCD power had to be applied later than LCD logic.
1. Set REG[03h] bit 3, LCDPWR Override, to "1" (ensures that LCD power is disabled).
2. Enable LCD logic. This is done by either setting GPIO0 to 0 for hardware power save
mode and/or by setting REG[03h] bits 1-0, software power save, to "11".
3. Count "x" Vertical Non-Display Periods.
"x" corresponds the length of time LCD logic must be enabled before LCD power-up,
converted to the equivalent vertical non-display periods. For example, at 72 HZ count-
ing 36 non-display periods results in a one half second delay.
4. Set REG[03h] bit 3 to "0" (enable LCD Power).
Power Off/Disable Sequence
The following is the recommended sequence for manually powering-down an LCD panel.
These steps would be used if power supply timing requirements were larger than the
timings built into the SED1374 power disable sequence.
1. Set REG[03h] bit 3, LCDPWR Override, to "1" (disables LCD Power).
2. Count "x" Vertical Non-Display Periods.
"x" corresponds to the power supply discharge time converted to the equivalent verti-
cal non-display periods.
3. Disable the LCD logic by setting the software power save in REG[03h] or setting
hardware power save via GPIO0.
Programming Notes and Examples
Issue Date: 99/04/27
SED1374
X26A-G-002-02