SED1374 Datasheet, PDF (325/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 11
Two other configuration options (CNF[4:3]) are also made at time of hardware reset:
• endian mode setting (big endian or little endian).
• polarity of the LCDPWR signal.
The capability to select the endian mode independent of the host bus interface offers more
flexibility in configuring the SED1374 with other CPUs.
For details on configuration, refer to the SED1374 Hardware Functional Specification,
document number X26A-A-001-xx.
3.2 Generic #1 Interface Mode
Generic #1 interface mode is the most general and least processor-specific interface mode
on the SED1374. The Generic # 1 interface mode was chosen for this interface due to the
simplicity of its timing.
The interface requires the following signals:
• BUSCLK is a clock input which is required by the SED1374 host interface. It is separate
from the input clock (CLKI) and is typically driven by the host CPU system clock.
• The address inputs AB0 through AB15, and the data bus DB0 through DB15, connect
directly to the CPU address and data bus, respectively. On 32-bit big endian architec-
tures such as the Power PC, the data bus would connect to the high-order data lines; on
little endian hosts, or 16-bit big endian hosts, they would connect to the low-order data
lines. The hardware engineer must ensure that CNF3 selects the proper endian mode
upon reset.
• Chip Select (CS#) is driven by decoding the high-order address lines to select the proper
IO or memory address space.
• WE0# and WE1# are write enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is writing data to the SED1374. These signals must
be generated by external hardware based on the control outputs from the host CPU.
• RD# and RD/WR# are read enables for the low-order and high-order bytes, respectively,
to be driven low when the host CPU is reading data from the SED1374. These signals
must be generated by external hardware based on the control outputs from the host CPU.
• WAIT# is a signal output from the SED1374 that indicates the host CPU must wait until
data is ready (read cycle) or accepted (write cycle) on the host bus. Since host CPU
accesses to the SED1374 may occur asynchronously to the display update, it is possible
that contention may occur in accessing the SED1374 internal registers and/or refresh
memory. The WAIT# line resolves these contentions by forcing the host to wait until the
resource arbitration is complete. This signal is active low and may need to be inverted if
the host CPU wait state signal is active high.
• The Bus Status (BS#) signal is not used in the bus interface for Generic #1 mode.
However, BS# is used to configure the SED1374 for Generic #1 mode and should be
tied low (connected to GND).
Interfacing to the PC Card Bus
Issue Date: 98/12/10
SED1374
X26A-G-009-02