SED1374 Datasheet, PDF (248/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 16
Epson Research and Development
Vancouver Design Center
6.5 Clock Input Support
The input clock (CLKI) frequency can be up to 50.0MHz for the SED1374 if the internal
clock divide by 2 is set. If the clock divide is not used, the maximum CLKI frequency is
25MHz.
A 25.0MHz oscillator (U2, socketed) is provided as the default clock source.
6.6 LCD Panel Voltage Setting
The SDU1374B0C board supports both 3.3V and 5.0V LCD panels through the single LCD
connector J5. The voltage level is selected by setting jumper J4 to the appropriate position.
Refer to Table 2-3: “Jumper Settings,” on page 9 for setting this jumper.
6.7 Monochrome LCD Panel Support
The SED1374 directly supports 4 and 8-bit, dual and single, monochrome passive LCD
panels. All necessary signals are provided on the 40-pin ribbon cable header J5. The
interface signals on the cable are alternated with grounds to reduce crosstalk and noise.
Refer to Table 3-1: “LCD Signal Connector (J5) Pinout,” on page 10 for specific
connection information.
6.8 Color Passive LCD Panel Support
The SED1374 directly supports 4 and 8, dual and single, color passive LCD panels. All the
necessary signals are provided on the 40-pin ribbon cable header J5. The interface signals
on the cable are alternated with grounds to reduce crosstalk and noise.
Refer to Table 3-1: “LCD Signal Connector (J5) Pinout,” on page 10 for specific
connection information.
6.9 Color TFT/D-TFD LCD Panel Support
The SED1374 directly supports 9 and 12-bit active matrix color TFT/D-TFD panels. All
the necessary signals can also be found on the 40-pin LCD connector J5. The interface
signals on the cable are alternated with grounds to reduce crosstalk and noise.
Refer to Table 3-1: “LCD Signal Connector (J5) Pinout,” on page 10 for connection infor-
mation.
SED1374
X26A-G-005-01
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26