SED1374 Datasheet, PDF (365/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 9
BCLK0
TS
TA
TIP
A[31:0]
R/W
SIZ[1:0], TT[1:0]
D[31:0]
Transfer Start
Wait States
Transfer
Complete
Sampled when TA low
Next Transfer
Starts
Figure 2-1: MCF5307 Memory Read Cycle
BCLK0
TS
TA
TIP
A[31:0]
R/W
SIZ[1:0], TT[1:0]
D[31:0]
Transfer Start
Valid
Wait States
Transfer
Complete
Next Transfer
Starts
Figure 2-2: MCF5307 Memory Write Cycle
2.1.3 Burst Cycles
Burst cycles are very similar to normal cycles, except that they occur as a series of four
back-to-back, 32-bit memory reads or writes, with the TIP (Transfer In Progress) output
asserted continuously through the burst. Burst memory cycles are mainly intended to facil-
itate cache line fill from program or data memory; they are typically not used for transfers
to or from IO peripheral devices such as the SED1374. The MCF5307 chip selects provide
a mechanism to disable burst accesses for peripheral devices which are not able to support
them.
Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 99/01/05
SED1374
X26A-G-011-02