SED1374 Datasheet, PDF (27/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 19
Pin Names
Type
WE0#
I
WE1#
I
CS#
I
BCLK
I
BS#
I
RD/WR#
I
Pin #
77
78
74
71
75
79
RESET#
Cell
State
Description
This pin has multiple functions.
CS
Input
• For SH-3/SH-4 mode, this pin inputs the write enable
signal for the lower data byte (WE0#).
• For MC68K #1, this pin must be tied to IO V_DD
• For MC68K #2, this pin inputs the bus size bit 0 (SIZ0).
• For Generic #1, this pin inputs the write enable signal for
the lower data byte (WE0#).
• For Generic #2, this pin inputs the write enable signal
(WE#)
See “Host Bus Interface Pin Mapping” for summary.
This pin has multiple functions.
CS
Input
• For SH-3/SH-4 mode, this pin inputs the write enable
signal for the upper data byte (WE1#).
• For MC68K #1, this pin inputs the upper data strobe
(UDS#).
• For MC68K #2, this pin inputs the data strobe (DS#).
• For Generic #1, this pin inputs the write enable signal for
the upper data byte (WE1#).
• For Generic #2, this pin inputs the byte enable signal for
the high data byte (BHE#).
See “Host Bus Interface Pin Mapping” for summary.
C
Input This pin inputs the chip select signal.
C
Input This pin inputs the system bus clock.
This pin has multiple functions.
• For SH-3/SH-4 mode, this pin inputs the bus start signal
(BS#).
CS
Input
• For MC68K #1, this pin inputs the address strobe (AS#).
• For MC68K #2, this pin inputs the address strobe (AS#).
• For Generic #1, this pin must be tied to V_SS.
• For Generic #2, this pin must be tied to IO V_DD.
See “Host Bus Interface Pin Mapping” for summary.
This pin has multiple functions.
• For SH-3/SH-4 mode, this pin inputs the RD/WR# signal.
The SED1374 needs this signal for early decode of the
bus cycle.
CS
Input
• For MC68K #1, this pin inputs the R/W# signal.
• For MC68K #2, this pin inputs the R/W# signal.
• For Generic #1, this pin inputs the read command for the
upper data byte (RD1#).
• For Generic #2, this pin must be tied to IO V_DD.
See “Host Bus Interface Pin Mapping” for summary.
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02