SED1374 Datasheet, PDF (29/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 21
Pin Name
FPLINE
FPSHIFT
LCDPWR
DRDY
Type
O
O
O
O
Pin #
38
28
43
42
RESET#
Cell
State
Description
CN3
0
Line Pulse
CN3
0
Shift Clock
CO1
0 if CNF4
1 if CNF4
=1
=0
LCD
Power
Control
This pin has multiple functions.
CN3
0
• TFT/MD-TFD Display Enable (DRDY).
• LCD Backplane Bias (MOD).
• Second Shift Clock (FPSHIFT2).
See “LCD Interface Pin Mapping” for summary.
5.2.3 Clock Input
Pin Name
CLKI
Type
I
Pin #
51
Driver
C Input Clock
Description
5.2.4 Miscellaneous
Pin Name
CNF[4:0]
GPIO0
TESTEN
Type
I
I/O,
I
I
Pin #
Cell
45, 46, 47,
48, 49
C
22
CS/
TS1
44
CD
RESET#
State
Description
As set by
hardware
Input
These inputs are used to configure the SED1374 - see
“Summary of Configuration Options”.
Must be connected directly to IO V_DD or V_SS.
This pin has multiple functions - see REG[03h] bit 2.
• General Purpose Input/Output pin.
• Hardware Power Save.
High
Impedance
Test Enable input. This input must be connected to V_SS.
5.2.5 Power Supply
Pin Name
COREVDD
IOVDD
VSS
Type
P
P
P
Pin #
1, 21, 41,
61
10, 29, 52
20, 27, 40,
50, 60, 72,
80
Driver
P
Core V_DD
P
IO V_DD
P
Common V_SS
Description
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02