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SED1374 Datasheet, PDF (401/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller
EPSON Research and Development
Vancouver Design Center
Page 11
3.2 Memory Mapping and Aliasing
The SED1374 requires an addressing space of 64K bytes while the SED1375 requires
128K. The on-chip display memory occupies the range 0 through 9FFFh. The registers
occupy the range FFE0h through FFFFh. The TMPR3912/22U demultiplexed address lines
A16 and above are ignored if the SED1374 is used, thus it is aliased 1024 times at 64K byte
intervals over the 64M byte PC Card slot #1 memory space. If the SED1375 is used, address
lines A17 and above are ignored; therefore the SED1375 is aliased 512 times at 128K byte
intervals. The TMPR3912/22U control signal CARDREG# is ignored; therefore the
SED1374 also takes up the entire PC Card slot #1 configuration space.
Note
If aliasing is undesirable, additional decoding circuitry must be added.
3.3 SED1374/75 Configuration and Pin Mapping
The SED1374/75 host bus interface is configured at power up by latching the state of the
CNF[3:0] pins. Pin BS# also plays a role in host bus interface configuration. One additional
configuration pin for the SED1374, CNF4, is also used to set the polarity of the LCDPWR
signal.
The table below shows the configuration pin connections to configure the SED1374/75 for
use with the TMPR3912/22U microprocessor.
SED1374
Configuration
Pin
BS#
CNF3
CNF[2:0]
Table 3-1: SED1374/75 Configuration for Generic #2 Bus Interface
Value hard wired on this pin is used to configure:
1 (IO VDD)
Generic #2
Big Endian
111: Generic #1 or #2
0 (VSS)
Generic #1
Little Endian
= configuration for Toshiba TMPR3912/22U host bus interface
When the SED1374/75 is configured for Generic #2 bus interface mode, the host interface
pins are mapped as in the table below.
Table 3-2: SED1374/75 Generic #2 Interface Pin Mapping
Pin Name Pin Function
WE1#
BHE#
BS#
RD/WR#
RD#
Connect to IO VDD
Connect to IO VDD
RD#
WE0#
WE#
SDU1374/75-TMPR3912/22U CPU Module
Issue Date: 98/12/23
X00A-G-004-01