SED1374 Datasheet, PDF (50/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 42
Epson Research and Development
Vancouver Design Center
Sync Timing
Frame Pulse
Line Pulse
DRDY (MOD)
Data Timing
Line Pulse
Shift Pulse
FPDAT[7:4]
t1
t2
t4
t3
t5
t6
t7
t8
t14
t9
t11 t10
t12 t13
1
2
Figure 7-15: Single Color 4-Bit Panel A.C. Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
Parameter
Frame Pulse setup to Line Pulse falling edge
Frame Pulse hold from Line Pulse falling edge
Line Pulse period
Line Pulse pulse width
MOD delay from Line Pulse rising edge
Shift Pulse falling edge to Line Pulse rising edge
Shift Pulse falling edge to Line Pulse falling edge
Line Pulse falling edge to Shift Pulse falling edge
Shift Pulse period
Shift Pulse pulse width low
Shift Pulse pulse width high
FPDAT[7:4] setup to Shift Pulse falling edge
FPDAT[7:4] hold to Shift Pulse falling edge
Line Pulse falling edge to Shift Pulse rising edge
Min
Typ
note 2
9
note 3
9
1
note 4
note 5
t14 + 0.5
1
0.5
0.5
0.5
0.5
23
1. Ts
2. t1_min
3. t3_min
4. t6_min
5. t7_min
= pixel clock period
= t3_min - 9Ts
= [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
= [(REG[08h] bits 4-0) x 8 + 0.5]Ts
= [(REG[08h] bits 4-0) x 8 + 9.5]Ts
Max
Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29