SED1374 Datasheet, PDF (323/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 9
During a read cycle, OE# (output enable) is driven low. A write cycle is specified by
driving OE# high and driving the write enable signal (WE#) low. The cycle can be
lengthened by driving WAIT# low for the time needed to complete the cycle.
Figure 2-1: and Figure 2-2: illustrate typical memory access cycles on the PC Card bus.
A[25:0]
REG#
ADDRESS VALID
CE1#
CE2#
OE#
WAIT#
D[15:0]
Hi-Z
Transfer Start
Hi-Z
DATA VALID
Transfer Complete
Figure 2-1: PC Card Read Cycle
A[25:0]
REG#
CE1#
CE2#
OE#
ADDRESS VALID
WE#
WAIT#
D[15:0]
Hi-Z
Transfer Start
Hi-Z
DATA VALID
Transfer Complete
Figure 2-2: PC Card Write Cycle
Interfacing to the PC Card Bus
Issue Date: 98/12/10
SED1374
X26A-G-009-02