SED1374 Datasheet, PDF (38/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 30
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7.1.3 Motorola M68K #1 Interface Timing
CLK
T_CLK
A[15:1]
CS#
R/W#
t1
AS#
VALID
UDS#, LDS#
INVALID
DTACK#
D[15:0]
(write
D[15:0]
(read)
t3
Hi-Z
Hi-Z
Hi-Z
t4
t7
t9
t10
VALID
VALID
t2
t6
t5
t8
t11
Hi-Z
Hi-Z
Hi-Z
Figure 7-3: M68K #1 Bus Timing (MC68000)
Symbol
f_CLK
T_CLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Table 7-3: M68K #1 Bus Timing (MC68000)
Parameter
Bus Clock Frequency
Bus Clock period
A[15:1], CS# valid before AS# falling edge
A[15:1], CS# hold from AS# rising edge
AS# low to DTACK# driven high
CLK to DTACK# low
AS# high to DTACK# high
AS# high to DTACK# high impedance
UDS#, LDS# falling edge to D[15:0] valid (write cycle)
D[15:0] hold from AS# rising edge (write cycle)
UDS#, LDS# falling edge to D[15:0] driven (read cycle)
D[15:0] valid to DTACK# falling edge (read cycle)
UDS#, LDS# rising edge to D[15:0] high impedance
Min
0
1/f_CLK
0
0
0
0
Max
33
16
15
20
T_CLK
T_CLK
15
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
CLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 86
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29