SED1374 Datasheet, PDF (265/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

EPSON Research and Development
Vancouver Design Center
Page 9
2.2 Memory Mapping and Aliasing
The SED1374 requires an addressing space of 64K bytes. The on-chip display memory occupies the
range 0 through 9FFFh. The registers occupy the range FFE0h through FFFFh. The TX3912
demultiplexed address lines A16 and above are ignored, thus the SED1374 is aliased 1024 times at
64K byte intervals over the 64M byte PC Card slot #1 memory space. In this example
implementation, the TX3912 control signal CARDREG* is ignored, the SED1374 also takes up the
entire PC Card slot 1 configuration space.
Note
If aliasing is undesirable, additional decoding circuitry must be added.
2.3 SED1374 Configuration and Pin Mapping
The SED1374 is configured at power up by latching the state of the CNF[4:0] pins. Pin BS# also
plays a role in host bus interface configuration. For details on configuration, refer to the SED1374
Hardware Functional Specification, document number X26A-A-001-xx.
The table below shows those configuration settings relevant to the direct connection approach.
SED1374
Configuration
Pin
BS#
CNF3
CNF[2:0]
Table 2-1: SED1374 Configuration for Direct Connection
Value hard wired on this pin is used to configure:
1 (IO V_DD)
Generic #2
Big Endian
111: Generic #1 or #2
0 (V_SS)
Generic #1
Little Endian
= configuration for Toshiba TX3912 host bus interface
When the SED1374 is configured for “Generic #2” interface, the host interface pins are mapped as
in the table below.
Table 2-2: SED1374 Generic #2 Interface Pin Mapping
Pin Name Pin Function
WE1#
BHE#
BS#
RD/WR#
RD#
Connect to IO V_DD
Connect to IO V_DD
RD#
WE0#
WE#
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
SED1374
X26A-G-004-01