SED1374 Datasheet, PDF (43/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
7.3 Display Interface
7.3.1 Power On/Reset Timing
Page 35
RESET#
REG[03h] bits [1:0]
LCDPWR
(CNF4 = 1)
LCDPWR
(CNF4 = 0)
FPLINE
FPSHIFT
FPDAT
FPFRAME
DRDY
00
11
t1
t2
ACTIVE
Figure 7-8: LCD Panel Power On/Reset Timing
Symbol
t1
t2
Parameter
REG[03h] to FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY
active
FPLINE, FPFRAME, FPSHIFT, FPDAT, DRDY active to
LCDPWR
Min Typ
0
Max
T_FPFRAME
Units
ns
Frames
Note
Where T_FPFRAME is the period of FPFRAME and T_PCLK is the period of the pixel clock.
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02