SED1374 Datasheet, PDF (94/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 86
Epson Research and Development
Vancouver Design Center
RESET#
Software Power Save
REG[03h] bits [1:0]
00
11
or
Hardware Power Save
00
11
LCDPWR
(CNF4 = Low)
LCDPWR
(CNF4 = Hi)
Panel Interface
Output Signals
(except LCDPWR)
Power Save Mode
0 frame
power-up
127 frames
power-down
Figure 13-1: Panel On/Off Sequence
0 frame
power-up
After chip reset, LCDPWR is inactive and the rest of the panel interface output signals are
held ‘low’. Software initializes the chip (i.e. programs the registers) and then - as a last step
set - programs REG[03h] bits [1:0] to 11. This starts the power-up sequence as shown. The
power-up/power-down sequence delay is 127 frames.
The power-up/power-down sequence also occurs when exiting/entering Software Power
Save Mode.
13.5 Turning Off BCLK Between Accesses
BCLK may be turned off (held low) between accesses if the following rules are observed:
1. BCLK must be turned off/on in a glitch free manner
2. BCLK must continue for a period equal to [8T_BCLK + 12T_MCLK] after the end of the
access (RDY# asserted or WAIT# deasserted).
3. BCLK must be present for at least one T_BCLK before the start of an access.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29