SED1374 Datasheet, PDF (415/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
4 8-Bit Processor to SED1374 Interface
Page 11
4.1 Hardware Description
The interface between the SED1374 and an 8-bit processor requires minimal glue logic. A
decoder is used to generate the chip select for the SED1374 based on where the SED1374
is mapped into memory. Alternatively, if the processor supports a chip select module, it can
be programmed to generate a chip select for the SED1374 without the need of an address
decoder.
An inverter inverts A0 to generate the Byte High Enable signal for the SED1374. If the
8-bit host interface has an active high WAIT signal, it must be inverted as well.
In order to support an 8-bit microprocessor with a 16-bit peripheral, the low and high order
bytes of the data bus must be connected together. The following diagram shows a typical
implementation of an 8-bit processor to SED1374 interface.
Generic 8-bit Bus
A[15:0]
D[7:0]
WAIT#
WE#
RD#
A0
BUSCLK
Decoder
SED1374
AB[15:0]
DB[7:0]
DB[15:8]
CS#
IO V_DD
System RESET
WAIT#
WE0#
RD#
BHE# (WE1#)
RD/WR#
BS#
BUSCLK
RESET#
Note:
When connecting the SED1374 RESET# pin, the system designer should be aware of all
conditions that may reset the SED1374 (e.g. CPU reset can be asserted during wake-up
from power-down modes, or during debug states).
Figure 4-1: Typical Implementation of an 8-bit Processor to the SED1374 Generic #2 Interface
Interfacing to an 8-bit Processor
Issue Date: 99/05/04
SED1374
X26A-G-013-01