SED1374 Datasheet, PDF (31/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
5.5 LCD Interface Pin Mapping
Page 23
SED1374
Pin Name
FPFRAME
FPLINE
FPSHIFT
DRDY
FPDAT0
FPDAT1
FPDAT2
FPDAT3
FPDAT4
FPDAT5
FPDAT6
FPDAT7
FPDAT8
FPDAT9
FPDAT10
FPDAT11
Table 5-3: LCD Interface Pin Mapping
Monochrome Passive Panel
4-bit
Single
8-bit
8-bit Dual
Single
MOD
driven 0
driven 0
driven 0
driven 0
D0
D1
D2
D3
GPIO1
GPIO2
GPIO3
GPIO4/
HW Video
Invert
MOD
D0
D1
D2
D3
D4
D5
D6
D7
GPIO1
GPIO2
GPIO3
GPIO4/
HW Video
Invert
MOD
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
GPIO1
GPIO2
GPIO3
GPIO4/
HW Video
Invert
4-bit
Single
MOD
driven 0
driven 0
driven 0
driven 0
D0
D1
D2
D3
GPIO1
GPIO2
GPIO3
GPIO4/
HW Video
Invert
Color Passive Panel
8-bit
8-bit
Single
Single
Format 1 Format 2
FPFRAME
FPLINE
FPSHIFT
FPSHIFT2 MOD
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
GPIO1
GPIO1
GPIO2
GPIO2
GPIO3
GPIO3
GPIO4/ GPIO4/
HW Video HW Video
Invert
Invert
8-bit Dual
MOD
LD0
LD1
LD2
LD3
UD0
UD1
UD2
UD3
GPIO1
GPIO2
GPIO3
GPIO4/
HW Video
Invert
Color TFT/MD-TFD
9-bit
12-bit
DRDY
R2
R3
R1
R2
R0
R1
G2
G3
G1
G2
G0
G1
B2
B3
B1
B2
B0
B1
GPIO2
R0
GPIO3
G0
GPIO4
B0
Note
1. Unused GPIO pins must be connected to IO V_DD.
2. Hardware Video Invert is enabled on FPDAT11 by REG[02h] bit 1.
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02