SED1374 Datasheet, PDF (47/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
7.3.4 Single Monochrome 8-Bit Panel Timing
Page 39
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
VDP
VNDP
LINE1 LINE2 LINE3 LINE4
LINE479 LINE480
LINE1 LINE2
FPLINE
DRDY (MOD)
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
1-1 1-9
1-2 1-10
1-3 1-11
1-4 1-12
1-5 1-13
1-6 1-14
1-7 1-15
1-8 1-16
HDP
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
For this timing diagram Mask FPSHIFT, REG[01h] bit 3, is set to 1
HNDP
1-633
1-634
1-635
1-636
1-637
1-638
1-639
1-640
Figure 7-12: Single Monochrome 8-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02