SED1374 Datasheet, PDF (59/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
7.3.10 9/12-Bit TFT/MD-TFD Panel Timing
Page 51
FPFRAME
FPLINE
FPDAT[11:0] LINE480
DRDY
VNDP₂
VDP
VNDP₁
LINE1
LINE480
FPLINE
FPSHIFT
HNDP₂
DRDY
FPDAT[9]
FPDAT[2:0]
FPDAT[10]
FPDAT[4:3]
FPDAT[11]
FPDAT[8:6]
Note: DRDY is used to indicate the first pixel
Example Timing for 640x480 panel
HDP
HNDP₁
1-1
1-2
1-1
1-2
1-1
1-2
1-640
1-640
1-640
Figure 7-24: 12-Bit TFT/MD-TFD Panel Timing
VDP =
VNDP =
VNDP1 =
VNDP2 =
HDP =
HNDP =
HNDP1=
HNDP2=
Vertical Display Period
Vertical Non-Display Period
Vertical Non-Display Period 1
Vertical Non-Display Period 2
Horizontal Display Period
Horizontal Non-Display Period
Horizontal Non-Display Period 1
Horizontal Non-Display Period 2
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= VNDP1 + VNDP2 = (REG[0Ah] bits 5-0) Lines
= REG[09h] bits 5-0 Lines
= (REG[0Ah] bits 5-0) - (REG[09Ah] bits 5-0) Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= HNDP1 + HNDP2 = (REG[08h] + 4) x 8Ts
= ((REG[07h] bits4-0) x 8) +16Ts
= (((REG[08h] bits4-0) - (REG[07h] bits 4-0)) x 8) +16Ts
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02