SED1374 Datasheet, PDF (39/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
7.1.4 Motorola M68K #2 Interface Timing
CLK
A[15:0]
CS#
SIZ0, SIZ1
R/W#
AS#
T_CLK
t1
VALID
DS#
DSACK1#
D[31:16]
(write)
D[31:16]
(read)
t3
t4
Hi-Z
t7
Hi-Z
t9
Hi-Z
VALID
VALID
Figure 7-4: M68K #2 Timing (MC68030)
Page 31
t2
t6
t5
t8
t10
Hi-Z
Hi-Z
Hi-Z
Symbol
f_CLK
T_CLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Table 7-4: M68K #2 Timing (MC68030)
Parameter
Bus Clock frequency
Bus Clock period
A[15:0], CS#, SIZ0, SIZ1 valid before AS# falling edge
A[15:0], CS#, SIZ0, SIZ1 hold from AS#, DS# rising edge
AS# low to DSACK1# driven high
CLK to DSACK1# low
AS# high to DSACK1# high
AS# high to DSACK1# high impedance
DS# falling edge to D[31:16] valid (write cycle)
AS#, DS# rising edge to D[31:16] invalid (write cycle)
D[31:16] valid to DSACK1# low (read cycle)
AS#, DS# rising edge to D[31:16] high impedance
Min
0
1/f_CLK
0
0
0
0
Max
33
22
18
26
T_CLK
T_CLK / 2
20
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Note
CLK may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 86
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02