SED1374 Datasheet, PDF (130/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 34
Epson Research and Development
Vancouver Design Center
6 LCD Power Sequencing and Power Save Modes
6.1 LCD Power Sequencing
LCD Power Sequencing allows the LCD power supply to discharge prior to shutting down
the LCD logic signals. Power sequencing is required to prevent long term damage to the
panel and to avoid unsightly “lines” on power-down and power-up.
The SED1374 performs automatic power sequencing when the LCD is enabled or disabled
through the Power Save bits in REG[03h] or in response to a hardware power save request.
For most applications the internal power sequencing is the appropriate choice.
Proper LCD power sequencing dictates there must be a time delay between the LCD power
being disabled and the LCD signals being shut down. During power-up the LCD signals
must be active prior to or when power is applied to the LCD. The time intervals vary
depending on the power supply design.
One frame after a power save mode has been enabled the SED1374 disables LCD power.
One hundred and twenty seven frames later the LCD logic signals are disabled. There may
be situations where the internal time delay is insufficient to discharge the LCD power
supply before the LCD signals are shut down. This section details the sequences to
manually power-up and power-down the LCD interface.
During the power up sequence the LCD power should not be applied before the LCD logic
signals. Usually the power and logic can begin at the same time. There may be times when
the LCD logic signals must begin before LCD power is applied.
6.2 Registers
REG[03h] Mode Register 2
LCDPWR
Override
Hardware
Power Save
Enable
Software
Power Save
bit 1
Software
Power Save
bit 0
The LCD Power (LCDPWR) Override bit forces LCD power to inactive one frame after
being toggled. The LCD logic signals to the panel are still active and are controlled by
enabling or disabling a power save mode. After enabling a power save mode there are still
128 frames before LCD logic signals are disabled.
The Hardware Power Save Enable bit must be set in order for a hardware power save
request (on GPIO0) to have any affect. Without enabling this bit toggling GPIO0 will have
no power save effect.
The Software Power Save bits are used to set the software power save mode. The two valid
states are "00" for power save and "11" for normal operation.
SED1374
X26A-G-002-02
Programming Notes and Examples
Issue Date: 99/04/27