SED1374 Datasheet, PDF (267/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

EPSON Research and Development
Vancouver Design Center
Page 11
The “Generic #1” host interface control signals of the SED1374 are asynchronous with respect to
the SED1374 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on pixel and frame rates,
power budget, part count and maximum SED1374 respective clock frequencies. Also, internal
SED1374 clock dividers provide additional flexibility.
3.2 IT8368E Configuration
The IT8368E provides eleven multi-function IO pins (MFIO). The IT8368E must have both “Fix
Attribute/IO” and “VGA” modes on. When both these modes are enabled, the MFIO pins provide
control signals needed by the SED1374 host bus interface, and a 16M byte portion of the system PC
Card attribute and IO space is allocated to address the SED1374. When accessing the SED1374 the
associated card-side signals are disabled in order to avoid any conflicts.
For mapping details, refer to section 3.3: “Memory Mapping and Aliasing.” For connection details
see Figure 3-1: “SED1374 to TX3912 Connection Using an IT8368E,” on page 10. For further infor-
mation on the IT8368E, refer to the IT8368E PC Card/GPIO Buffer Chip Specification.
Note
When a second IT8368E is used, that circuit should not be set in VGA mode.
Interfacing to the Toshiba MIPS TX3912 Processor
Issue Date: 98/11/09
SED1374
X26A-G-004-01