SED1374 Datasheet, PDF (52/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 44
Epson Research and Development
Vancouver Design Center
Sync Timing
Frame Pulse
Line Pulse
t1
t2
t4
t3
Data Timing
Line Pulse
t6a
t6b
t7a
t8
t14
t9
t11 t10
Shift Pulse 2
Shift Pulse
FPDAT[7:0]
t7b
t12 t13 t12 t13
1
2
Figure 7-17: Single Color 8-Bit Panel A.C. Timing (Format 1)
Symbol
Parameter
Min
Typ
t1 Frame Pulse setup to Line Pulse falling edge
note 2
t2 Frame Pulse hold from Line Pulse falling edge
9
t3 Line Pulse period
note 3
t4 Line Pulse pulse width
9
t6a Shift Pulse falling edge to Line Pulse rising edge
note 4
t6b Shift Pulse 2 falling edge to Line Pulse rising edge
note 5
t7a Shift Pulse 2 falling edge to Line Pulse falling edge
note 6
t7b Shift Pulse falling edge to Line Pulse falling edge
note 7
t8 Line Pulse falling edge to Shift Pulse rising, Shift Pulse 2 falling edge t14 + 2
t9 Shift Pulse 2, Shift Pulse period
4
t10 Shift Pulse 2, Shift Pulse pulse width low
2
t11 Shift Pulse 2, Shift Pulse pulse width high
2
t12 FPDAT[7:0] setup to Shift Pulse 2, Shift Pulse falling edge
1
t13 FPDAT[7:0] hold to Shift Pulse 2, Shift Pulse falling edge
1
t14 Line Pulse falling edge to Shift Pulse rising edge
23
Max
Units
(note 1)
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
Ts
1. Ts = pixel clock period
2. t1_min = t3_min - 9Ts
3. t3_min = [((REG[04h] bits 6-0)+1) x 8 + ((REG[08h] bits 4-0) + 4) x 8]Ts
4. t6a_min = [(REG[08h] bits 4-0) x 8 + t13 - t10]Ts
5. t6b_min = [(REG[08h] bits 4-0) x 8 + t13]Ts
6. t7a_min = [(REG[08h] bits 4-0) x 8 + 11]Ts
7. t7b_min = [(REG[08h] bits 4-0) x 8 + 11] - t10]Ts
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29