SED1374 Datasheet, PDF (37/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 29
Symbol
f_CKIO
T_CKIO
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
Table 7-2: SH-3 Bus Timing
Parameter
Bus Clock frequency
Bus Clock period
Clock pulse width high
Clock pulse width low
A[15:0], RD/WR# setup to CKIO
A[15:0], RD/WR# hold from CS#
BS# setup
BS# hold
CSn# setup
Falling edge RD# to DB[15:0] driven
Rising edge CSn# to WAIT# high impedance
Falling edge CSn# to WAIT# driven
CKIO to WAIT# delay
DB[15:0] setup to 2^nd CKIO after BS# (write cycle)
DB[15:0] hold from rising edge of WEn# (write cycle)
DB[15:0] valid to RDY# falling edge setup time (read cycle)
Rising edge RD# to DB[15:0] high impedance (read cycle)
a _{One Software WAIT State Required}
Min
0
1/f_CKIO
17
16
0
0
5
5
0
0
0
0
Max^a
50
25
10
15
20
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
CKIO may be turned off (held low) between accesses - see Section 13.5, “Turning Off
BCLK Between Accesses” on page 86
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02