SED1374 Datasheet, PDF (326/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 12
4 PC Card to SED1374 Interface
Epson Research and Development
Vancouver Design Center
4.1 Hardware Connections
The SED1374 is interfaced to the PC Card interface with a minimal amount of glue logic.
A PAL is used to decode the write and read signals of the PC Card bus to generate RD#,
RD/WR#, WE0#, WE1#, and CS# for the SED1374. The PAL also inverts the reset signal
of the PC card since it is active high and the SED1374 uses an active low reset. For PAL
equations for this implementation refer to Section 4.3, “PAL Equations” on page 14.
In this implementation, the address inputs (AB[15:0]) and data bus (DB[15:0] connect
directly to the CPU address (A[15:0]) and data bus (D[15:0]).
The PC Card interface does not provide a bus clock, so one must be supplied for the
SED1374. Since the bus clock frequency is not critical, nor does it have to be synchronous
to the bus signals, it may be the same as CLKI.
BS# (bus start) is not used by Generic #1 mode but is used to configure the SED1374 for
Generic #1 and should be tied low (connected to GND).
The following diagram shows a typical implementation of the PC Card to SED1374
interface.
PC Card socket
OE#
WE#
CE1#
CE2#
REG#
RESET
PAL16L8-15
SED1374
RD#
RD/WR#
WE0#
WE1#
CS#
RESET#
A[15:0]
D[15:0]
WAIT#
15K pull-up
Oscillator
AB[15:0]
DB[15:0]
WAIT#
BUSCLK
CLKI
Figure 4-1: Typical Implementation of PC Card to SED1374 Interface
SED1374
X26A-G-009-02
Interfacing to the PC Card Bus
Issue Date: 98/12/10