SED1374 Datasheet, PDF (62/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 54
8 Registers
Epson Research and Development
Vancouver Design Center
8.1 Register Mapping
The SED1374 registers are located in the upper 32 bytes of the 64K byte SED1374 address
range. The registers are accessible when CS# = 0 and AB[15:0] are in the range FFE0h
through FFFFh.
8.2 Register Descriptions
Unless specified otherwise, all register bits are reset to 0 during power up.
REG[00h] Revision Code Register
Address = FFE0h
Product Code Product Code Product Code Product Code Product Code Product Code
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision
Code Bit 1
Read Only
Revision
Code Bit 0
bits 7-2
bits 1-0
Product Code
This is a read-only register that indicates the product code of the chip. The product code is
000110.
Revision Code
This is a read-only register that indicates the revision code of the chip. The revision code is
00.
REG[01h] Mode Register 0
Address = FFE1h
TFT/STN Dual/Single Color/Mono
FPLine
Polarity
FPFrame
Polarity
Mask
FPSHIFT
Read/Write.
Data Width
Bit 1
Data Width
Bit 0
bit 7
TFT/STN
When this bit = 0, STN (passive) panel mode is selected. When this bit = 1, TFT/MD-TFD
panel mode is selected. If TFT/MD-TFD panel mode is selected, Dual/Single (REG[01h]
bit 6) and Color/Mono (REG[01h] bit5) are ignored. See Table 8-1: “Panel Data Format”
below.
bit 6
Dual/Single
When this bit = 0, Single LCD panel drive is selected. When this bit = 1, Dual LCD panel
drive is selected. See Table 8-1: “Panel Data Format” below.
bit 5
Color/Mono
When this bit = 0, Monochrome LCD panel drive is selected. When this bit = 1, Color
LCD panel drive is selected. See Table 8-1: “Panel Data Format” below.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29