SED1374 Datasheet, PDF (71/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 63
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REG[13h] Screen 1 Vertical Size Register (LSB)
Address = FFF3h
Screen 1
Vertical Size
Bit 7
Screen 1
Vertical Size
Bit 6
Screen 1
Vertical Size
Bit 5
Screen 1
Vertical Size
Bit 4
Screen 1
Vertical Size
Bit 3
Screen 1
Vertical Size
Bit 2
Screen 1
Vertical Size
Bit 1
Read/Write
Screen 1
Vertical Size
Bit 0
REG[14h] Screen 1 Vertical Size Register (MSB)
Address = FFF4h
n/a
n/a
n/a
n/a
n/a
Read/Write
Screen 1
Screen 1
n/a
Vertical Size Vertical Size
Bit 9
Bit 8
REG[14h] bits 1-0
REG[13h] bits 7-0
Screen 1 Vertical Size Bits [9:0]
This register is used to implement the Split Screen feature of the SED1374. These bits
determine the height (in lines) of Screen 1. On reset this register is set to 0h.
In landscape modes, if this register is programmed with a value, n, where n is less than the
Vertical Panel Size (REG[06h], REG[05h]), then lines 0 to n of the panel contain Screen 1
and lines n+1 to REG[06h], REG[05h] of the panel contain Screen 2. See Figure 8-1:
“Screen-Register Relationship, Split Screen,” on page 64. If Split Screen is not desired,
this register must be programmed greater than, or equal to the Vertical Panel Size,
REG[06h] and REG[05h].
In SwivelView modes this register must be programmed greater than, or equal to the Verti-
cal Panel Size, REG[06h] and REG[05h]. See “SwivelView™” on page 79.
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02