SED1374 Datasheet, PDF (66/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 58
Epson Research and Development
Vancouver Design Center
REG[03h] Mode Register 2
Address = FFE3h
Look-Up
Table Bypass
n/a
n/a
Read/Write
n/a
LCDPWR
Override
Hardware
Power Save
Enable
Software
Power Save
Bit 1
Software
Power Save
Bit 0
bit 7
Look-Up Table Bypass
When the Look-Up Table Bypass bit = 0, the Green Look-Up Table is used for display
data output in gray shade modes. When this bit = 1, the Look-Up Table is bypassed for dis-
play data output in gray shade modes (for power save purposes). See “Look-Up Table
Architecture” on page 72.
There is no effect on changing this bit in color modes. In color display mode the Look-Up
Table cannot be bypassed.
bit 3
LCDPWR Override
This bit is used to override the panel on/off sequencing logic. When this bit = 0, LCDPWR
and the panel interface signals are controlled by the sequencing logic. When this bit 1,
LCDPWR is forced to off and the panel interface signals are forced low immediately upon
entering power save mode. See Section 7.3.2, “Power Down/Up Timing” on page 36 for
further information.
bit 2
Hardware Power Save Enable
When this bit = 1 GPIO0 is used as the Hardware Power Save input pin. When this bit = 0
GPIO0 operates normally.
Table 8-5: Hardware Power Save/GPIO0 Operation
RESET#
State
0
Hardware Power
Save Enable
REG[03h] bit 2
X
GPIO0 Config
REG[18h] bit 0
X
1
0
0
1
0
1
1
0
1
1
1
X
GPIO0
Status/Control
REG[19h] bit 0
X
reads pin status
0
1
X
GPIO0 Operation
GPIO0 Input
(high impedance)
GPIO0 Output = 0
GPIO0 Output = 1
Hardware Power Save
Input (active high)
bits 1-0
Software Power Save Bits [1: 0]
These bits select the Power Save Mode as shown in the following table.
Table 8-6: Software Power Save Mode Selection
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Mode
Software Power Save
reserved
reserved
Normal Operation
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29