SED1374 Datasheet, PDF (177/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

SED1374 Register Summary
REG[00h] REVISION CODE REGISTER ¹ IO address = FFE0h ², RO
Product Code = 000110
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision Code = 00
Bit 1
Bit 0
REG[13h] SCREEN 1 VERTICAL SIZE REGISTER (LSB) IO address = FFF3h, RW
Screen 1 Vertical Size = (REG[13h], REG[14h])
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[01h] MODE REGISTER 0 IO address = FFE1h, RW
TFT/STN
Dual/Single Color/Mono³
FPLine
Polarity
FPFrame
Polarity
Mask
FPSHIFT
Data Width ⁴
Bit 1
Bit 0
REG[02h] MODE REGISTER 1 IO address = FFE2h, RW
Bit-Per-Pixel ³
Bit 1
Bit 0
High ⁵ Input Clock Display
Performance Div (CLKI/2) Blank
Frame
Repeat
Hw Video
Invert
Enable
Software
Video Invert
REG[03h] MODE REGISTER 2 IO address = FFE3h, RW
Look-Up
Table Bypass
n/a
n/a
n/a
LCDPWR
Override
Hardware
PS Enable
Sw Power Save ⁶
Bit 1
Bit 0
REG[04h] HORIZONTAL PANEL SIZE REGISTER IO address = FFE4h, RW
Horizontal Panel Size = 8(REG + 1)
n/a
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[05h] VERTICAL PANEL SIZE REGISTER (LSB) IO address = FFE5h, RW
Vertical Panel Size = (REG[05h], REG[06h]) + 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[06h] VERTICAL PANEL SIZE REGISTER (MSB) IO address = FFE6h, RW
n/a
n/a
n/a
n/a
n/a
n/a
Vertical Panel Size
Bit 9
Bit 8
REG[07h] FPLINE START POSITION IO address = FFE7h, RW
FPLine Start Position = 8(REG[07h] + 2)
n/a
n/a
n/a
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[08h] HORIZONTAL NON-DISPLAY PERIOD IO address = FFE8h, RW
Horizontal Non-Display Period = 8(REG + 4)
n/a
n/a
n/a
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[09h] FPFRAME START POSITION IO address = FFE9h, RW
FPFrame Start Position
n/a
n/a
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[0Ah] VERTICAL NON-DISPLAY PERIOD REGISTER IO address = FFEAh, RW
Vert Non-
Disp Status
n/a
Bit 5
Bit 4
Vertical Non-Display Period
Bit 3
Bit 2
Bit 1
Bit 0
REG[0Bh] MOD RATE REGISTER IO address = FFEBh, RW
MOD Rate
n/a
n/a
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[0Ch] SCREEN 1 START WORD ADDRESS REGISTER (LSB) IO address = FFECh, RW
Screen 1 Start Word Address = (REG[0Ch], REG[0Dh])
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[0Dh] SCREEN 1 START WORD ADDRESS REGISTER (MSB) IO address = FFEDh, RW
reserved
Bit 14
Bit 13
Screen 1 Start Word Address
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
REG[14h] SCREEN 1 VERTICAL SIZE REGISTER (MSB) IO address = FFF4h, RW
n/a
n/a
n/a
n/a
n/a
n/a
Screen 1 Vertical Size
Bit 9
Bit 8
REG[15h] LOOK-UP TABLE ADDRESS REGISTER ⁷ IO address = FFF5h, RW
RGB Index
Look-Up Table Address
n/a
n/a
Bit 1
Bit 0
Bit 3
Bit 2
Bit 1
Bit 0
REG[16h] LOOK-UP TABLE BANK SELECT REGISTER IO address = FFF6h, RW
Red Bank Select
Green Bank Select
n/a
n/a
Bit 1
Bit 0
Bit 1
Bit 0
Blue Bank Select
Bit 1
Bit 0
REG[17h] LOOK-UP TABLE DATA REGISTER IO address = FFF7h, RW
Look-Up Table Data
n/a
n/a
n/a
n/a
Bit 3
Bit 2
Bit 1
Bit 0
REG[18h] GPIO CONFIGURATION CONTROL REGISTER IO address = FFF8h, RW
n/a
n/a
n/a
GPIO4 Pin GPIO3 Pin GPIO2 Pin
IO Config IO Config IO Config
GPIO1 Pin
IO Config
GPIO0 Pin
IO Config
REG[19h] GPIO STATUS / CONTROL REGISTER IO address = FFF9h, RW
n/a
n/a
n/a
GPIO4 Pin GPIO3 Pin GPIO2 Pin
IO Status IO Status IO Status
GPIO1 Pin
IO Status
GPIO0 Pin
IO Status
REG[1Ah] SCRATCH PAD REGISTER IO address = FFFAh, RW
Scratch Pad Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[1Bh] SWIVELVIEW MODE REGISTER IO address = FFFBh, RW
SwivelView SwivelView
Mode En. Mode Sel.
n/a
n/a
n/a
reserved
SwivelView Mode PCLK
Select
Bit 1
Bit 0
REG[1Ch] LINE BYTE COUNT REGISTER IO address = FFFCh, RW
Line Byte Count
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Notes
1 These bits are used to identify the SED1373 at power on / reset.
2 IO addresses are relative to the beginning of display memory.
3 Gray Shade/Color Mode Selection
Color/Mono
REG[01] bit 5
Bit-Per-Pixel Bit 1
REG[02] bit 7
Bit-Per-Pixel Bit 0
REG[02] bit 6
Display Mode
0
1
1
0
2 Colors
1 Bit-Per-Pixel
1
4 Colors
2 Bit-Per-Pixel
0
16 Colors
4 Bit-Per-Pixel
1
256 Colors
8 Bit-Per-Pixel
0
0
1
0
2 Gray Shade
1 Bit-Per-Pixel
1
4 Gray Shade
2 Bit-Per-Pixel
0
16 Gray Shade
4 Bit-Per-Pixel
1
reserved
REG[0Fh] SCREEN 2 START WORD ADDRESS REGISTER (LSB) IO address = FFEFh, RW
Screen 2 Start Word Address = (REG[0F], REG[10h])
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REG[10h] SCREEN 2 START WORD ADDRESS REGISTER (MSB) IO address = FFF0h, RW
Screen 2 Start Word Address
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
REG[12h] MEMORY ADDRESS OFFSET REGISTER IO address = FFF2h, RW
Memory Address Offset
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
4 Panel Data Format
TFT/STN
REG[01]
bit 7
Color/
Mono
REG[01]
bit 5
0
0
1
1
Dual/
Single
REG[01]
bit 6
0
Data
Width
Bit 1
REG[01]
bit 1
0
1
0
1
1
0
0
1
0
1
1
don’t care
X26A-R-001-02
Data
Width
Bit 0
REG[01]
bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
Mono Single 4-bit LCD
Mono Single 8-bit LCD
reserved
reserved
reserved
Mono Dual 8-bit LCD
reserved
reserved
Color Single 4-bit LCD
Color Single 8-bit LCD Format 1
reserved
Color Single 8-bit LCD Format 2
reserved
Color Dual 8-bit LCD
reserved
reserved
9 bit TFT Panel
12 bit TFT Panel
5 High Performance Selection
High Performance
Bit-Per-Pixel
Bit 1
REG[02] bit 7
0
0
1
1
X
Bit-Per-Pixel
Bit 0
REG[02] bit 6
0
1
0
1
X
Display Modes
MClk = PClk/8
1 bit-per-pixel
MClk = PClk/4
2 bit-per-pixel
MClk = PClk/2
4 bit-per-pixel
MClk = PClk
8 bit-per-pixel
MClk = PClk
6 Power Save Mode Selection
Power Save Bit 1
0
0
1
1
Power Save Bit 0
0
1
0
1
Mode
Software Power Save Mode
reserved
reserved
Normal Operation
7 Look-Up Table Access
Color/Mono
REG[01h]
bit 5
0
1
1
1
1
REG[15h]
bit 5
bit 4
X
X
0
0
0
1
1
0
1
1
Look-Up Table Selected
Pointer Sequence
Green/Gray Look-Up Table
Auto-Increment
Red Look-Up Table
Green/Gray Look-Up Table
Blue Look-Up Table
G[n], G[n+1], G[n+2]...
R[n], G[n], B[n] R[n+1], G[n+1],...
R[n], R[n+1], R[n+2]...
G[n], G[n+1], G[n+2]...
B[n], B[n+1], B[n+2]...
Page 1
99/04/23