SED1374 Datasheet, PDF (72/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

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Epson Research and Development
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(REG[0Dh], REG[0Ch]) Words
Line 0 Last Pixel Address + REG[12h] Words
Line 0
Line 1
Line 0 Last Pixel Address=((REG[0Dh], REG[0Ch]) +
(8(REG[04h]+1) × BPP/16))
Words
Image 1
((REG[06h], REG[05])+1) Lines
Image 2
Line=(REG[14h], REG[13h])
(REG[10h], REG[0Fh]) Words
8(REG[04h]+1) Pixels
Where:
(REG[0Dh], REG[0Ch]) is the Screen 1 Start Word Address
BPP is Bits-per-Pixel as set by REG[02h] bits 7:6
REG[12h] is the Address Pitch Adjustment in Words
(REG[10h], REG[0Fh]) is the Screen 2 Start Word Address
(REG[14h], REG[13h]) is the Screen 1 Vertical Size
(REG[06h], REG[05h]) is the Vertical Panel Size
Virtual Image
REG[12h] Words
Figure 8-1: Screen-Register Relationship, Split Screen
Consider an example where REG[14h], REG[13h]= 0CEh for a 320x240 display system.
The upper 207 lines (CEh + 1) of the panel show an image from the Screen 1 Start Word
Address. The remaining 33 lines show an image from the Screen 2 Start Word Address.
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29