SED1374 Datasheet, PDF (250/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 18
Epson Research and Development
Vancouver Design Center
6.13 CPU/Bus Interface Header Strips
All of the CPU/Bus interface pins of the SED1374 are connected to the header strips H1
and H2 for easy interface to a CPU/Bus other than ISA.
Refer to Table 4-1: “CPU/BUS Connector (H1) Pinout,” on page 11 and Table 4-2:
“CPU/BUS Connector (H2) Pinout,” on page 12 for specific settings.
Note
These headers only provide the CPU/Bus interface signals from the SED1374. When
another host bus interface is selected by CNF[3:0] and BS#, appropriate external decode
logic MUST be used to access the SED1374. Refer to Table 5-1: “Host Bus Interface
Pin Mapping,” on page 13 for connection details.
SED1374
X26A-G-005-01
SDU1374B0C Rev. 1.0 ISA Bus Evaluation Board User Manual
Issue Date: 98/10/26