SED1374 Datasheet, PDF (63/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
Page 55
bit 4
bit 3
bit 2
bits 1-0
FPLINE Polarity
This bit controls the polarity of FPLINE in TFT/MD-TFD mode (no effect in passive
panel mode). When this bit = 0, FPLINE is active low. When this bit = 1, FPLINE is active
high.
FPFRAME Polarity
This bit controls the polarity of FPFRAME in TFT/MD-TFD mode (no effect in passive
panel mode). When this bit = 0, FPFRAME is active low. When this bit = 1, FPFRAME is
active high.
Mask FPSHIFT
FPSHIFT is masked during non-display periods if either of the following two criteria is
met:
1. Color passive panel is selected (REG[01h] bit 5 = 1)
2. This bit (REG[01h] bit 2) = 1
Data Width Bits [1:0]
These bits select the display data format. See Table 8-1: “Panel Data Format” below.
Table 8-1: Panel Data Format
TFT/STN
REG[01h] bit 7
Color/Mono Dual/Single
REG[01h] bit 5 REG[01h] bit 6
Data Width
Bit 1
REG[01h] bit 1
0
0
1
0
0
1
1
0
0
0
1
1
0
1
1
1
X (don’t care)
Data Width
Bit 0
REG[01h] bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Function
Mono Single 4-bit passive LCD
Mono Single 8-bit passive LCD
reserved
reserved
reserved
Mono Dual 8-bit passive LCD
reserved
reserved
Color Single 4-bit passive LCD
Color Single 8-bit passive LCD format 1
reserved
Color Single 8-bit passive LCD format 2
reserved
Color Dual 8-bit passive LCD
reserved
reserved
9-bit TFT/MD-TFD panel
12-bit TFT/MD-TFD panel
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02