SED1374 Datasheet, PDF (57/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Epson Research and Development
Vancouver Design Center
7.3.9 Dual Color 8-Bit Panel Timing
FPFRAME
FPLINE
DRDY (MOD)
FPDAT[7:0]
LINE 1/241 LINE 2/242
Page 49
VDP
VNDP
LINE 239/479 LINE 240/480
LINE 1/241
FPLINE
DRDY (MOD)
HDP
FPSHIFT
FPDAT7
FPDAT6
FPDAT5
FPDAT4
FPDAT3
FPDAT2
FPDAT1
FPDAT0
1-R1 1-G2 1-B 3 1-R 5 1-G6 1-B7
1-G1 1-B2 1-R4 1-G5 1-B6 1-R8
1-B1 1-R 3 1-G4 1-B5 1-R7 1-G8
1-R2 1-G3 1-B4 1-R6 1-G7 1-B8
241-R1 241-G2 241-B3 241-R5 241-G6 241-B7
241-G1 241-B2 241-R 4 241-G 5 241-B6 241-R8
241-B1 241-R3 241-G4 241-B5 241-R7 241-G8
241-R 2 241-G3 241-B4 241-R 6 241-G7 241-B8
* Diagram drawn with 2 FPLINE vertical blank period
Example timing for a 640x480 panel
HNDP
1 -B 6 3 9
1 -R 6 4 0
1-G640
1 -B 6 4 0
241-
B639
241-
R640
241-
G640
241-
B640
Figure 7-22: Dual Color 8-Bit Panel Timing
VDP =
VNDP =
HDP =
HNDP =
Vertical Display Period
Vertical Non-Display Period
Horizontal Display Period
Horizontal Non-Display Period
= (REG[06h] bits 1-0, REG[05h] bits 7-0) + 1 Lines
= REG[0Ah] bits 5-0 Lines
= ((REG[04h] bits 6-0) + 1) x 8Ts
= (REG[08h] + 4) x 8Ts
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02