SED1374 Datasheet, PDF (382/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 8
EPSON Research and Development
Vancouver Design Center
2 Direct Connection to the Philips PR31500/PR31700
2.1 General Description
In this example implementation the SED1374 occupies the PR31500/PR31700 PC Card slot #1.
The SED1374 is easily interfaced to the PR31500/PR31700 with minimal additional logic. The
address bus of the PR31500/PR31700 PC Card interface is multiplexed and can be demultiplexed
using an advanced CMOS latch (e.g., 74ACT373). The direct connection approach makes use of the
SED1374 in its “Generic Interface #2” configuration.
The following diagram demonstrates a typical implementation of the interface.
PR31500/PR31700
/RD
/WE
/CARD1CSL
/CARD1CSH
ENDIAN
ALE
A[12:0]
D[31:24]
D[23:16]
/CARD1WAIT
DCLKOUT
Latch
V_{DD pull-up}
Clock divider
+3.3V
SED1374
IO V_DD, CORE V_DD
RD#
WE#
IO V_DD
IO V_DD
System RESET
BHE#
BS#
RD/WR#
RESET#
CS#
AB[15:13]
AB[12:0]
DB[7:0]
DB[15:8]
...or...
Oscillator
See text
WAIT#
CLKI
BCLK
Figure 2-1: SED1374 to PR31500/PR31700 Direct Connection
The “Generic #2” host interface control signals of the SED1374 are asynchronous with respect to
the SED1374 bus clock. This gives the system designer full flexibility to choose the appropriate
source (or sources) for CLKI and BCLK. The choice of whether both clocks should be the same, and
whether to use DCLKOUT (divided) as clock source, should be based on the desired:
• pixel and frame rates.
• power budget.
• part count.
• maximum SED1374 clock frequencies.
The SED1374 also has internal clock dividers providing additional flexibility.
SED1374
X26A-G-012-01
Interfacing to the Philips MIPS PR31500/PR31700 Processor
Issue Date: 98/11/09