 English |
|
|
|
|
|
|
|
| SED1374 Datasheet, PDF (308/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller | |||
| |||
| ◁ |
Page 12
Epson Research and Development
Vancouver Design Center
refresh memory. The WAIT# line resolves these contentions by forcing the host to wait
until the resource arbitration is complete. This signal is active low and may need to be
inverted if the host CPU wait state signal is active high.
⢠The Bus Status (BS#) and Read/Write (RD/WR#) signals are not used in the bus inter-
face for Generic #2 mode. However, BS# is used to configure the SED1374 for
Generic #2 mode and should be tied high (connected to IO VDD). RD/WR# should also
be tied high.
SED1374
X26A-G-008-04
Interfacing to the NEC VR4102⢠Microprocessor
Issue Date: 99/01/05
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese