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SED1374 Datasheet, PDF (19/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller | |||
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Epson Research and Development
Vancouver Design Center
Page 11
2.4 Display Modes
⢠SwivelViewâ¢: direct 90° hardware rotation of display image for portrait mode display.
⢠1/2/4 bit-per-pixel (bpp), 2/4/16-level grayshade display.
⢠1/2/4/8 bit-per-pixel, 2/4/16/256-level color display.
⢠Up to 16 shades of gray by FRM on monochrome passive LCD panels; a 16x4 Look-
Up-Table is used to map 1/2/4-bpp modes into these shades.
⢠256 simultaneous of 4096 colors on color passive and active matrix LCD panels; three
16x4 Look-Up Tables are used to map 1/2/4/8-bpp modes into these colors.
⢠Split screen display for all landscape panel modes allows two different images to be
simultaneously displayed.
⢠Virtual display support (displays images larger than the panel size through the use of
panning).
2.5 Clock Source
⢠Maximum operating clock (CLK) frequency of 25MHz.
⢠Operating clock (CLK) is derived from CLKI input.
CLK = CLKI
or
CLK = CLKI/2
⢠Pixel Clock (PCLK) and Memory Clock (MCLK) are derived from CLK.
2.6 Miscellaneous
⢠Hardware/Software Video Invert.
⢠Software Power Save mode.
⢠Hardware Power Save mode.
⢠LCD power-down sequencing.
⢠5 General Purpose Input/Output pins are available.
⢠GPIO0 is available if Hardware Power Save is not required.
⢠GPIO[4:1] are available if upper LCD data pins (FPDAT[11:8]) are not required for
TFT/MD-TFD support or Hardware Video Invert.
⢠IO Operates from 3.0 volts to 5.5 volts
⢠Core operates from 3.0 volts to 3.6 volts.
2.7 Package
⢠80 pin QFP14 package.
Hardware Functional Specification
Issue Date: 99/04/29
SED1374
X26A-A-001-02
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