SED1374 Datasheet, PDF (42/420 Pages) Epson Company – SED1374 Embedded Memory Color LCD Controller

Page 34
7.2 Clock Input Requirements
Clock Input Waveform
tPWH
90%
VIH
VIL
10%
tr
tPWL
tf
TCLKI
Figure 7-7: Clock Input Requirements
Epson Research and Development
Vancouver Design Center
Symbol
f_CLKI
T_CLKI
t_PWH
t_PWL
t_f
t_r
Table 7-7: Clock Input Requirements
Parameter
Input Clock Frequency (CLKI)
Input Clock period (CLKI)
Input Clock Pulse Width High (CLKI)
Input Clock Pulse Width Low (CLKI)
Input Clock Fall Time (10% - 90%)
Input Clock Rise Time (10% - 90%)
Min
0
1/f_CLKI
8
8
Max
50
5
5
Units
MHz
ns
ns
ns
ns
Note
When CLKI is > 25MHz it must be divided by 2 (REG[02h] bit 4 = 1).
SED1374
X26A-A-001-02
Hardware Functional Specification
Issue Date: 99/04/29